Field effect transistors (FET's) employing compound semiconductors, such as gallium arsenide (GaAs) or indium phosphide (InP) are useful as high frequency transistors because electron mobilities in these compound semiconductors are relatively high.
Recently, FET's having a gate electrode formed in a recess of an active layer have been employed to realize a high breakdown voltage and high speed operation.
A method for fabricating a conventional FET having a gate electrode formed in a stepped recess of an active layer (hereinafter referred to as a stepped recess gate structure) is illustrated in FIGS. 7(a) and 7(c). In FIG. 7C, a semi-insulating substrate 1 is formed of GaAs or the like. An active layer 2 is formed on a surface of the substrate 1. A source electrode 3 and a drain electrode 4 are formed of metal in ohmic contact with the substrate 1. Reference numerals 7 7a, and 7b designate an upper stepped recess and reference numeral 9 designates a lower stepped recess. Resists 6a and 6b are used for forming the upper stepped recess 7 and resists 10a and 10b are used for forming the lower stepped recess 9. Gate electrode metal 11a, 11b and 11c form A Schottky contact with the substrate 1 and a gate electrode 11 is produced from the gate electrode metal 11a.
The fabricating method will be described.
First, as shown in FIG. 7(a), an active layer 2 is produced at a desired position in a semi-insulating substrate 1 by ion implantation or epitaxial growth. Then, a source electrode 3 and a drain electrode 4 are formed on the active layer 2 in ohmic contact with the active layer 2 and patterns of photoresist 6a and 6b are formed for etching a part of the active layer 2 between the source electrode 3 and the drain electrode 4. Then, an upper stepped recess 7 is formed by etching.
Next, as shown in FIG. 7(b), patterns of photoresist 10a and 10b are formed for further etching a part of the active layer 2 at the surface of the upper stepped recess 7 and then a lower stepped recess 9 is formed. Thereafter, gate electrode metals 11b, 11c and 11a are deposited on the resist patterns 10a and 10b and the lower stepped recess 9, respectively, separated from each other.
Next, as shown in FIG. 7(c), the resist patterns 10a and 10b and the gate electrode metals 11b and 11c are removed by lift-off leaving gate electrode metal 11a as the gate electrode 11 on the lower stepped recess 9. Thus, an FET having a stepped recess gate structure is completed.
In this fabricating method, alignment of the resist patterns 6a and 6b and 10a and 10b with the substrate 1 is shifted to some degree by the exposure apparatus. For example, as shown in FIG. 7(c), when the distance between an end of the source electrode 3 and the upper stepped recess 7 and the distance between an end of the drain electrode 4 and the upper stepped recess 7 are indicated by a and b, respectively, and the width of the upper stepped recess 7 on the side of the source electrode 3 and the width of the upper stepped recess 7 on the side of the drain electrode 4 are indicated by c and d, respectively, even when the condition that a=b and c=d is required, the following relations EQU .vertline.a-b.vertline..ltoreq..alpha. EQU .vertline.c-d.vertline..ltoreq..alpha.
result due to the shift of alignment, where +a is mask alignment precision of the exposure apparatus.
When .alpha.=.+-.0.3 micron, in order to satisfy the condition that a, b, c, d&gt;0, i.e., in order to prevent the source electrode 3 and the drain electrode 4 from overlapping with the pattern of the upper stepped recess 7, they should be spaced apart from each other by 2.alpha. (=0.6 micron) or more. Further, in order to prevent the patterns of the upper stepped recess 7 and the lower stepped recess 9 from overlapping, the width of the lower stepped recess 9 should be 2.alpha. (=0.6 micron) or more and the widths of the upper stepped recesses 7a and 7b should be 2.alpha. (=0.6 micron) or more. Overall, the source electrode 3 and the drain electrode 4 each have to be formed relative to the gate electrode 11 with an alignment margin of at least 4.alpha. (=1.2 micron). This is a great problem for a semiconductor device in which a good high frequency characteristic is desired.
In addition, the length of the gate electrode on the lower stepped recess 9 in the direction between the source electrode 3 and the drain electrode 4 is indicated by lg. Since a reduction in the gate length significantly contributes to improved speed and an improved high efficiency of shortening of the gate length is desired. However, according to the conventional fabricating method, since the gate electrode is formed by lift-off using the thick resist films 10a and 10b having an opening at the lower stepped recess 9 as a mask, the section of the gate electrode 11 gradually changes from a trapezoid to a triangle configuration with a reduction in the gate length lg, so that the gate area is reduced and the gate resistance is abruptly increased. This results in limitations on the increase in speed of the FET and also reduces in reliability due to heat generation at the gate electrode.
As described above, while the stepped recess FET is a structure that should enhance the breakdown voltage and efficiency and has generally been used for high power output FETs, the above-described fabrication steps for the conventional stepped recess FET have made it difficult to shorten the source electrode to gate electrode distance and the drain electrode to gate electrode distance due to the mask alignment precision of the exposure apparatus and to improve speed above a certain value. In addition, the miniaturization of the gate electrode 11 increases the gate resistance, thereby obstructing a high frequency operation and reliability is also reduced due to heat generation.